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FOD8001 ?high noise imm unity , 3.3v/5v logic gate optocoupler ?008 fairchild semiconductor corporation www.fairchildsemi.com FOD8001 rev. 1.0.3 december 2010 FOD8001 high noise immunity, 3.3v/5v logic gate optocoupler features high noise imm unity char acter iz ed b y common mode rejection (cmr) and p o w er supply rejection (psr) speci?ations ? 20kv/? minimum static cmr @ vcm = 1000v ? 25kv/? typical dynamic cmr @ vcm = 1500v, 20mbaud rate ? psr in excess of 10% of the supply voltages across full operating bandwidth high speed: ? 25mbit/sec date rate (nrz) ? 40ns max. propagation delay ? 6ns max. pulse width distortion ? 20ns max. propagation delay skew 3.3v and 5v cmos compatibility extended industr ial temper ate r ange , -40? to 105? temper ature r ange saf ety and regulator y pending appro v als: ? ul1577, 3750 vacrms for 1 min. ? iec60747-5-2 (pending) applications industrial fieldbus communications ? profibus, devicenet, can, rs485 programmable logic control isolated data acquisition system description the FOD8001 is a 3.3v/5v high-speed logic gate optocoupler, which supports isolated communications allowing digital signals to communicate between sys- tems without conducting ground loops or hazardous common mode rejection and power supply rejection specifications. this high-speed logic gate optocoupler, packaged in a compact 8-pin small outline package, consists of a high- speed algaas led driven by a cmos buffer ic coupled to a cmos detector ic. the detector ic comprises an integrated photodiode, a high-speed transimpedance amplifier and a voltage comparator with an output driver. the cmos technology coupled to the high efficiency of the led achieves low power consumption as well as very high speed (40ns propagation delay, 6ns pulse width distortion). related resources www.fairchildsemi.com/products/opto/ www.fairchildsemi.com/pf/fo/fod0721.html www.fairchildsemi.com/pf/fo/fod0720.html www.fairchildsemi.com/pf/fo/fod0710.html functional sc hematic 1 2 3 4 5 6 7 8 v dd2 nc v o gnd2 *: pin 3 m ust be left unconnected v dd1 v i * gnd1 v i h l v o h l led off on tr uth t a b l e voltages. it utilizes fairchild? p roprietary coplanar pack - ag ing technology, optoplanar , and optimized ic design to achieve high noise immunity, characterized by high
?008 fairchild semiconductor corporation www.fairchildsemi.com FOD8001 rev. 1.0.3 2 FOD8001 ?high noise immunity, 3.3v/5v logic gate optocoupler pin definitions absolute maximum ratings (t a = 25? unless otherwise speci?d.) stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. notes: 1. derate linearly from 25? at a rate of tbd w/? 2. derate linearly from 25? at a rate of tbd mw/?. 3. functional operation under these conditions is not implied. permanent damage may occur if the device is subjected to conditions outside these ratings. 4. 0.1? bypass capacitor must be connected between pin 1 and 4, and 5 and 8. pin number pin name pin function description 1v dd1 input supply voltage 2v i input data 3 led anode ?must be left unconnected 4 gnd1 input ground 5 gnd2 output ground 6v o output data 7n c not connected 8v dd2 output supply voltage symbol parameter value units t stg storage temperature -40 to +125 ? t opr operating temperature -40 to +105 ? t sol lead solder temperature (refer to re?w temperature pro?e) 260 for 10 sec ? v dd1 , v dd2 supply voltage 0 to 6.0 v v i input voltage -0.5 to v dd1 + 0.5 v i i input dc current -10 to +10 ? v o output voltage -0.5 to v dd2 + 0.5 v i o av erage output current 10 ma pd i input power dissipation (1)(3) 90 mw pd o t otal power dissipation (2)(3) 70 mw symbol parameter min. max. unit t a ambient operating temperature -40 +105 ? v dd1 , v dd2 supply voltages (3.3v operation) (4) 3.0 3.6 v supply voltages (5.0v operation) (4) 4.5 5.5 v ih logic high input voltage 2.0 v dd v v il logic low input voltage 0 0.8 v t r , t f input signal rise and fall time 1.0 ms
?008 fairchild semiconductor corporation www.fairchildsemi.com FOD8001 rev. 1.0.3 3 FOD8001 ?high noise immunity, 3.3v/5v logic gate optocoupler isolation characteristics (apply over all recommended conditions, typical value is measured at t a = 25?) notes: 5. device is considered a two terminal device: pins 1, 2, 3 and 4 are shorted together and pins 5, 6, 7 and 8 are shorted together. 6. 3,750 vac rms for 1 minute duration is equivalent to 4,500 vac rms for 1 second duration. electrical characteristics (apply over all recommended conditions, typical value is measured at v dd1 = v dd2 = +3.3v, v dd1 = +3.3v and v dd2 = +5.0v, v dd1 = +5.0v and v dd2 = +3.3v, v dd1 = v dd2 = +5.0v, t a = 25?) symbol characteristics test conditions min. typ.* max. unit v iso input-output isolation voltage f = 60hz, t = 1.0 min, i i-o 10? (5)(6) 3750 ? ? vac rms r iso isolation resistance v i-o = 500v (5) 10 11 ?? ? c iso isolation capacitance v i-o = 0v, f = 1.0mhz (5) ?0.2 ? pf symbol parameter conditions min. typ. max. units input characteristics i dd1l logic low input supply current v i = 0v 6.2 10.0 ma i dd1h logic high input supply current v i = v dd1 0.8 3.0 ma i ia , i ib input current -10 +10 ? output characteristics i dd2l logic low output supply current v i = 0v 4.5 9.0 ma i dd2h logic high output supply current v i = v dd1 4.5 9.0 ma v oh logic high output voltage i o = -20?, v i = v ih , v dd2 = +3.3v 2.9 3.3 v i o = -4ma, v i = v ih , v dd2 = +3.3v 1.9 2.9 i o = -20?, v i = v ih , v dd2 = +5.0v 4.4 5.0 i o = -4ma, v i = v ih , v dd2 = +5.0v 4.0 4.8 vo l logic low output voltage i o = 20?, v i = v il 0 0.1 v i o = 4ma, v i = v il 0.3 1.0
?008 fairchild semiconductor corporation www.fairchildsemi.com FOD8001 rev. 1.0.3 4 FOD8001 ?high noise immunity, 3.3v/5v logic gate optocoupler switching characteristics (apply over all recommended conditions, typical value is measured at v dd1 = v dd2 = +3.3v, v dd1 = +3.3v and v dd2 = +5.0v, v dd1 = +5.0v and v dd2 = +3.3v, v dd1 = v dd2 = +5.0v, t a = 25?) notes: 7. t psk is equal to the magnitude of the worst case difference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 8. common mode transient immunity at output high is the maximum tolerable positive dvcm/dt on the leading edge of the common mode impulse signal, vcm, to assure that the output will remain high. common mode transient immunity at output low is the maximum tolerable negative dvcm/dt on the trailing edge of the common pulse signal, vcm, to assure that the output will remain low. 9. unloaded dynamic power dissipation is calculated as follows: c pd x v dd x f + i dd + v pd where f is switched time in mhz. symbol parameter test conditions min. typ. max. unit t phl propagation delay time to logic low output c l = 15pf 25 40 ns t plh propagation delay time to logic high output c l = 15pf 25 40 ns pwd pulse width distortion, | t phl ?t plh | pwd = 40ns, c l = 15pf 2 6 ns data rate 25 mb/s t psk propagation delay skew c l = 15pf (7) 20 ns t r output rise time (10%?0%) 6.5 ns t f output fall time (90%?0%) 6.5 ns |cm h | common mode transient immunity at output high v i = v dd1 , v o > 0.8 v dd1 , v cm = 1000v (8) 20 40 kv/? |cm l | common mode transient immunity at output low v i = 0v, v o < 0.8v, v cm = 1000v (8) 20 40 kv/? c pdi input dynamic power dissipation capacitance (9) 30 pf c pdo output dynamic power dissipation capacitance (9) 3pf
?008 fairchild semiconductor corporation www.fairchildsemi.com FOD8001 rev. 1.0.3 5 FOD8001 ?high noise immunity, 3.3v/5v logic gate optocoupler typical performance curves 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 012345 v o -outputv oltage (v) v i -i nput voltage (v) v dd1 =v dd 2 =3.3v 1. 0 1. 2 1. 4 1. 6 1. 8 2. 0 3.0 3.5 4.0 4.5 5.0 5.5 v ith -typicalin put voltage swicthing threshold (v) v dd1 -i nput supply voltage (v) v dd2 =3.3v 5.5 6.0 6.5 7.0 7.5 -40 -20 0 20 4 06080100 t r -risetim e(ns) t a -ambientte m perat ur e ( c) fr equency = 12.5mhz duty c ycle = 50% v dd1 =v dd2 =3.3v 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 -40 -20 0 20 4 0608 0 100 t f -falltim e(ns) t a -ambientte mperat ure ( c) fr equency = 12.5mhz dut y c ycle = 50% v dd1 =v dd2 =3.3v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40 -20 0 20 4 06080100 pw d - pu lse width distortion (ns) t a a -ambi ent temperature ( c) fr equency = 12.5mhz dut y cycle = 50% v dd1 =v dd2 =3.3v 20 22 24 26 28 30 32 -40 -20 0 20 4 06080100 t p -p ro pagation delay (ns) t-ambientt emperat ur e ( c) t phl t plh fr equency = 12.5mhz duty c ycle = 50% v dd1 =v dd 2 =3.3v figure 1. typical output voltage vs. input voltage figure 2. input voltage switching threshold vs. input supply voltage figure 3. propogation delay vs. ambient temperature figure 4. pulse width distortion vs. ambient temperature figure 5. typical rise time vs. ambient temperature figure 6. typical fall time vs. ambient temperature
?008 fairchild semiconductor corporation www.fairchildsemi.com FOD8001 rev. 1.0.3 6 FOD8001 ?high noise immunity, 3.3v/5v logic gate optocoupler typical performance curves (continued) 22 24 26 28 30 32 34 15 20 25 30 35 40 45 50 55 t p -propaga tion d elay (ns) c l -out put load capacitance (pf) t phl t pl h fr e quency = 12.5mhz duty cycle = 50% v dd1 =v dd2 =3.3v 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 15 20 25 30 35 40 45 50 55 pwd - pulse wi dth dist ortion (ns) c l -out put load capacitance (pf) fr equency = 12.5mhz dut y c ycle = 50% v dd1 =v dd2 =3.3v 4 5 6 7 8 9 10 11 12 15 20 25 30 35 40 45 50 55 t r -risetim e(ns) c l -out put load capacitance (pf) fr equency = 12.5mhz dut y cycle = 50% v dd1 =v dd2 =3.3v 2 4 6 8 10 12 14 16 15 20 25 30 35 40 45 50 55 t f -falltim e(ns) c l -out put load capacitance (pf) freq uency = 1 2. 5mhz duty c ycle = 50% 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0 2000 4000 6000 8000 10000 12000 i dd1 -i n put supply current (ma) f-fre quency (khz) t a =105 c t a =25 c t a =-40 c v dd1 =5.5v 5. 0 5. 2 5. 4 5. 6 5. 8 6. 0 02 000 4000 6000 8000 10000 12000 i dd2 -o utput supply current (ma) f- freq uency (khz) v dd 1 =v dd2 =5.5v *pi n6floating t a =105 c t a =25 c t a =-40 c figure 7. typical propogation delay vs. output load capacitance figure 8. typical width distortion vs. output load capacitance figure 9. typical rise time vs. output load capacitance figure 10. typical fall time vs. output load capacitance figure 11. input supply current vs. frequency figure 12. output supply current vs. frequency v dd1 =v dd2 =3.3v
?008 fairchild semiconductor corporation www.fairchildsemi.com FOD8001 rev. 1.0.3 7 FOD8001 ?high noise immunity, 3.3v/5v logic gate optocoupler t est circuits figure 13. test circuit for propogation delay time and rise time, fall time figure 14. test circuit for instantaneous common mode rejection voltage v in t plh t r v out v ol 50% 90% 10% input output 3.3v 50% v oh t f t phl 1 2 v dd2 = 3.3v v o 0.1 f 0v?.3v c l 3 4 8 7 6 5 0.1 f v dd1 = 3.3v pulse width = 40ns duty cycle = 50% 1 2 v dd2 = 3.3v v o v cm + 0.1 f sw b a c l 3 4 8 7 6 5 0.1 f v dd1 = 3.3v v oh 0.8 x v dd switching pos. (a) v in = 3.3v switching pos. (b) v in = 0v gnd 1kv v ol v cm cm h cm l 0.8v
?008 fairchild semiconductor corporation www.fairchildsemi.com FOD8001 rev. 1.0.3 8 FOD8001 ?high noise imm unity , 3.3v/5v logic gate optocoupler application inf ormation noise is defined as any unwanted signal that degrades or interferes with the operation of a system or circuit. input-output noise rejection is a key characteristic of an optocoupler, and the performance specification for this noise rejection is called, ?ommon mode transient immunity or common mode rejection, cmr? the cmr test configuration is presented in high speed optocoupler datasheets, which tests the optocoupler to a specified rate of interfering signal (dv/dt), at a specified peak volt- age (vcm). this defined noise signal is applied to the test device while the coupler is a stable logic high or logic low state. this test procedure evaluates the interface device in a constant or static logic state. this type of cmr can be referred to as static cmr ? fairchild? high speed opto- couplers, which use an optically transparent, electrically conductive shield, and offer active totem pole logic out- put have static cmr in excess of 50kv/us at peak ampli- tudes of 1.5kv to 2.0kv. dynamic common mode rejection the noise susceptibility of an interface while it is actively transferring data is a common requirement in serial data communication. however, the static cmr specification is not adequate in quantifying the electrical noise suscepti- bility for optocouplers used in isolating high speed data transfer. a serial data communication network? noise perfor- mance is usually quantified as the number of bit errors per second or as a ratio of the number of bits transmitted in a specified time frame. this describes bit error rate, ber. test equipment that evaluates ber is called a bit error rate tester, bert. when a bert system is com- bined with a cmr tester, the active or dynamic noise rejection of an isolated interface can then be quantified. this type of cmr is thus defined as dynamic cmr ? therefore, evaluating the common mode rejection while the optocoupler is switching at high speed represents a realistic approach to understand noise interference. test circuit functions were built to interface a commercial pseudo-random bit sequence (prbs) generator and error detector with a pair of high speed optocouplers, FOD8001, connected in a loop-back configuration. with a 10mbaud prbs serial data stream, no error was detected until the common mode voltage rose above 2.5kv with a dv/dt of 45kv/us. and increasing the data rate beyond 10mbaud, the test was conducted at 20mbaud, and no error was detected at dv/dt of 25kv/us at common mode voltage of 1.5kv. the test data for the dynamic cmr is comparable or better than the static cmr specifications found in the datasheet. these excellent noise rejection performances are results of the innovative circuit design and the po wer suppl y noise rejection high levels of electrical noise can cause the optocoupler to register the incorrect logic state. the most commonly discussed noise signal is the common mode noise found between the input and output of the optocoupler. how- ever, common mode noise is not the only path of noise into the input or output of the optocoupler. due to the high gain and wide bandwidth of the transimpedance amplifier used for the photo detector circuits, power sup- ply noise can cause the optocoupler to change state independent of the led operation. power supply noise is typically characterized as either random or periodic pulses with varying amplitudes and rates of rise and fall. the necessary tests have been conducted to understand the influence of the power supply noise and its effect of the proper operation of the FOD8001. the optocoupler under test offered power supply noise rejection in excess of 10% of the supply voltage for a frequency ranging from 100khz to 35mhz, for logic high and logic low states. p roprietary coplanar assembly process.
?008 fairchild semiconductor corporation www.fairchildsemi.com FOD8001 rev. 1.0.3 9 FOD8001 ?high noise immunity, 3.3v/5v logic gate optocoupler small outline package dimensions note: all dimensions are in millimeters. pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ 0.024 (0.61) 0.050 (1.27) 0.155 (3.94) 0.275 (6.99) 0.060 (1.52) lead coplanarity : 0.004 (0.10) max 0.202 (5.13) 0.182 (4.63) 0.021 (0.53) 0.011 (0.28) 0.050 (1.27) typ 0.244 (6.19) 0.224 (5.69) 0.143 (3.63) 0.123 (3.13) 0.008 (0.20) 0.003 (0.08) 0.010 (0.25) 0.006 (0.16) seating plane 0.164 (4.16) 0.144 (3.66)
?008 fairchild semiconductor corporation www.fairchildsemi.com FOD8001 rev. 1.0.3 10 FOD8001 ?high noise immunity, 3.3v/5v logic gate optocoupler carrier tape specification note: all dimensions are in millimeters. ordering information all packages are lead free per jedec: j-std-020b standard. marking information option order entry identi?r description no suf? FOD8001 small outline 8-pin, shipped in tubes (50 units per tube) r2 FOD8001r2 small outline 8-pin, tape and reel (2,500 units per reel) 4.0 0.10 1.5 min user direction of feed 2.0 0.05 1.75 0.10 5.5 0.05 12.0 0.3 8.0 0.10 0.30 max 8.3 0.10 3.50 0.20 0.1 max 6.40 0.20 5.20 0.20 1.5 0.1/-0 1 2 5 3 4 de?itions 1 f airchild logo 2 device number 3 one digit year code, e.g., ? 4 tw o digit work week ranging from ?1 to ?3 5 assembly package code 8001 s1 yy x
?008 fairchild semiconductor corporation www.fairchildsemi.com FOD8001 rev. 1.0.3 11 FOD8001 ?high noise immunity, 3.3v/5v logic gate optocoupler reflow profile 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 temperature ( c) time (s) 0 60 180 120 270 260 c >245 c = 42 sec time above 183 c = 90 sec 360 1.822 c/sec ramp up rate 33 sec
?008 fairchild semiconductor corporation www.fairchildsemi.com FOD8001 rev. 1.0.3 12 tradem arks th e following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its global subsidiaries ,and is not in tended to be an exhaustive list of all such trademarks. a ccupower auto-spm build it now coreplus corepower crossvolt ctl cu rrent transfer logic deuxpeed dual cool ecospark e fficientmax esbc fair child fairchild semiconductor fa ct quiet series fact f ast fa stvcore fetbench flashwriter * fps f-pfs frfet global power resource sm green fps green fps e-series g max gto in tellimax isoplanar me gabuck mi crocoupler microfet mi cropak mi cropak2 m illerdrive moti onmax moti on-spm optohit optologic op toplanar pdp spm powe r-spm po we rtrench powerxs pr ogrammable active droop qfet qs quiet series r apidconfigure savi ng our world ,1mw/w/kwatatime si gnalwise sma rtmax smart start spm stealth s uperfet supe rsot -3 s upersot -6 s upersot -8 s upremos syncfet sy nc-lock * th ep ower franchise th er ight technology for your success tinyb oost tinybuck tiny calc ti nylogic tinyopto tinypower tinypwm tinywire trifault detect t ruecurrent * serdes uhc ultra frfet unifet vcx vi sualmax xs *t rademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fa i rchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers t hese products. li fe support policy fa i rchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are in tended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance wi th instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. an ti -counterfeiting policy fairchild semiconductor corporation's anti-counterfeiting policy. fairchild's anti-counterfeiting policy is also stated on our external websi te, www.fairchildsemi.com, under sales support. c ounterfeiting of semiconductor parts is a growing problem in the industry. all manufacturers of semiconductor products are experiencing counterf eiting of their parts. cu stomers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, faile da pplications, and increased cost of production and manufacturing delays. fairchild is taking strong measures to protect ourselves and our customers from the proli feration of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts either directly from fairchild or from authorized fairchi ld distribu tors who are lis ted by country on our web page cited above. products customers buy either from fairchild directly or from authorized fairchild distributors are ge nuine parts, have full traceability, meet fairchild's quality standards for handling and storage and provide access to fairchild's full range of up-to-date technica land product information. fairchild and our authorized distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. fairc hild will not provide any warranty coverage or other assistance for parts bought from unauthorized sources. fairchild is committed to combat this global problem and encou rage our customers to do their part in stopping this practice by buying direct or from authorized distributors. product status definitions defi nition of terms da tasheet identification product st atus definition ad vance information formative / in design datasheet contains the design specifi cations for product development. s pecifications may change in any manner without notice. pr eliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild se mi conductor reserves the right to make changes at any time without notice to improve design. no i dentification needed full production datasheet contains final specifications. fairchi ld semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product that is discontinued by fairchild semiconductor. th e datasheet is for reference information only. rev. i51 FOD8001 ?high noise immunity, 3.3v/5v logic gate optocoupler

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